![]() ![]() CACTI is an extension to previous models that includes a tag array model, nonstep stage input slopes, rectangular stacking of memory subarrays, a transistor-level decoder model, column-multiplexed bitlines, cycle times and access times, and others. It supports both direct mapped and associative caches. The earlier versions of CACTI modeled access and cycle times of on-chip caches. CACTI is an analytical model for a variety of cache components that contribute to the overall CPU memory subsystem. Perhaps the most widely used tool in this realm is the CACTI. Tomislav Janjusic, Krishna Kavi, in Advances in Computers, 2014 3.6.1 CACTI Although caches can be implemented in a myriad of different ways, this simple cache implementation serves as a usable, functional cache design. Finally, the cache controller is responsible for interfacing to the lower level of memory when the access misses in order to fill the cache. It is also responsible for facilitating other functions like multiporting through banking to control each access and keep track of bank collisions. In Figure 5.54, the cache controller has the responsibility of keeping track of cache operations and accesses to implement additional cache specifications like write-back/write-through behavior. Also, although the TLB access here is shown to be performed in parallel with the cache tag and data access, it can be performed at any time as long as the translation is available in time for use by the comparator. For systems that do not employ some form of virtual addressing, the TLB is optional, but otherwise it is needed, especially if physical addresses are stored in the tag area. For an N-way associative cache, we use N tag data pairs (note that these are logical pairs and that they are not necessarily implemented in the same memory array), an N-way comparator, and an N-way multiplexer to determine the proper data and to select it appropriately.
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